Switched-capacitor samplers of the general type used in, for example, the KAD5512P-50 12-bit, 500 Mega-Sample Per Second (MSPS) Analog-to-Digital Converter (ADC) available from Intersil Corporation can provide high performance and low-power consumption. However, these samplers sometimes suffer from degraded linearity at high input signal frequencies. Such high-frequency non-linearities can arise due to an input signal V(t) having a high derivative, (dV/dt).
One way in which a high input signal dV/dt can corrupt operation of such circuits is by imperfect bootstrapping of a series input switch that connects the sampler input to a plate (“top plate”) of a sampling capacitor. Another way is due to charge loss from the other capacitor plate (“bottom plate”), as a result of forward biasing or undesired partial turn-on of an associated Field Effect Transistor (FET) switch.
To the degree that dV/dt-related effects cause distortion of the ADC output, it is possible to improve on the performance by acquiring information about input signal dV/dt at the instants when the signal V(t) samples are acquired, and then using this information to correct the ADC result.
Algorithms implementing such corrections have been demonstrated. One approach, as described in U.S. Pat. No. 7,142,137 to Batruni and assigned to Optichron, Inc. uses an estimate of dV/dt that is digitally reconstructed from the digital output of the ADC. This method suffers from digital complexity and power consumption, and from the necessity of assumptions and constraints regarding the input signal spectrum—specifically, an assumption is made concerning which Nyquist zone the input signal occupies.
Researchers at Stanford University have published papers describing digital post-correction of sampler nonlinearity also using digital dV/dt estimation, but with a more specific sampler model than Optichron's method. See Nikaeen, P. and Murmann, B., “Digital Correction of Dynamic Track-and-Hold Errors Providing SFDR>83 dB up to fin=470 MHz, IEEE 2008 Custom Integrated Circuits Conference (2008) and is “Digital Compensation of Dynamic Acquisition Errors at the Front-end of High-Performance A/D Converters, IEEE Journal of Selected Topics in Signal Processing, Vol. 3. No. 3, June 2009, the entire contents of each of which are hereby incorporated by reference.